I am currently an PH.D. Student at Center for Energy-efficient Computing and Applications (CECA), Peking University. I obtained my bachelor degree in Computer Science from Peking University in 2021.
My research interests is currently about routing of ASICs and FPGAs.
J. Wang, X. Jiang, Y. Lin, "Top-Level Routing for Multiply-Instantiated Blocks with Topology Hashing" the 61th ACM/IEEE Design Automation Conference (DAC 2024). (Accepted)
J. Mai, J. Wang, Z. Di and Y. Lin, "Multielectrostatic FPGA Placement Considering SLICEL–SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 43, no. 2, pp. 641-653, Feb. 2024, doi: 10.1109/TCAD.2023.3313101.
J. Mai, J. Wang, Z. Di, G. Luo, Y. Liang and Y. Lin, "OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit," 2023 IEEE 15th International Conference on ASIC (ASICON)
J. Wang, J. Mai, Z. Di, Y. Lin, "A Robust FPGA Router with Concurrent Intra-CLB Rerouting." 2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC).
X. Jiang, J. Wang, Y. Lin, Z. Wang, "FPGA-Accelerated Maze Routing Kernel for VLSI Designs" 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC).
Y. Guo, J. Wang, J. Zhang, G. Luo, "Formulating Data-arrival Synchronizers in Integer Linear Programming for CGRA Mapping." the 58th ACM/IEEE Design Automation Conference (DAC 2021)
Introduction to Computing Fall 2021
Introduction to Computing Fall 2020